#ifndef __VDP_HAL_IP_MMU_H__
#define __VDP_HAL_IP_MMU_H__


#include "vdp_define.h"


HI_VOID VDP_MMU_SetPtwPf                 ( HI_U32 layer, HI_U32 ptw_pf                    ); 
HI_VOID VDP_MMU_SetIntEn                 ( HI_U32 layer, HI_U32 int_en                    ); 
HI_VOID VDP_MMU_SetGlbBypass             ( HI_U32 layer, HI_U32 glb_bypass                ); 
// HI_VOID VDP_MMU_SetSmmuIdle              ( HI_U32 layer, HI_U32 smmu_idle                 ); 
HI_VOID VDP_MMU_SetAutoClkGtEn           ( HI_U32 layer, HI_U32 auto_clk_gt_en            ); 
HI_VOID VDP_MMU_SetRfsRet1n              ( HI_U32 layer, HI_U32 rfs_ret1n                 ); 
HI_VOID VDP_MMU_SetRfsEma                ( HI_U32 layer, HI_U32 rfs_ema                   ); 
HI_VOID VDP_MMU_SetRfsEmaw               ( HI_U32 layer, HI_U32 rfs_emaw                  ); 
HI_VOID VDP_MMU_SetIntsTlbinvalidWrMsk   ( HI_U32 layer, HI_U32 ints_tlbinvalid_wr_msk    ); 
HI_VOID VDP_MMU_SetIntsTlbinvalidRdMsk   ( HI_U32 layer, HI_U32 ints_tlbinvalid_rd_msk    ); 
HI_VOID VDP_MMU_SetIntsPtwTransMsk       ( HI_U32 layer, HI_U32 ints_ptw_trans_msk        ); 
HI_VOID VDP_MMU_SetIntsTlbmissMsk        ( HI_U32 layer, HI_U32 ints_tlbmiss_msk          ); 
HI_VOID VDP_MMU_SetIntsTlbinvalidWrRaw   ( HI_U32 layer, HI_U32 ints_tlbinvalid_wr_raw    ); 
HI_VOID VDP_MMU_SetIntsTlbinvalidRdRaw   ( HI_U32 layer, HI_U32 ints_tlbinvalid_rd_raw    ); 
HI_VOID VDP_MMU_SetIntsPtwTransRaw       ( HI_U32 layer, HI_U32 ints_ptw_trans_raw        ); 
HI_VOID VDP_MMU_SetIntsTlbmissRaw        ( HI_U32 layer, HI_U32 ints_tlbmiss_raw          ); 
HI_VOID VDP_MMU_SetIntsTlbinvalidWrStat  ( HI_U32 layer, HI_U32 ints_tlbinvalid_wr_stat   ); 
HI_VOID VDP_MMU_SetIntsTlbinvalidRdStat  ( HI_U32 layer, HI_U32 ints_tlbinvalid_rd_stat   ); 
HI_VOID VDP_MMU_SetIntsPtwTransStat      ( HI_U32 layer, HI_U32 ints_ptw_trans_stat       ); 
HI_VOID VDP_MMU_SetIntsTlbmissStat       ( HI_U32 layer, HI_U32 ints_tlbmiss_stat         ); 
HI_VOID VDP_MMU_SetIntsTlbinvalidWrClr   ( HI_U32 layer, HI_U32 ints_tlbinvalid_wr_clr    ); 
HI_VOID VDP_MMU_SetIntsTlbinvalidRdClr   ( HI_U32 layer, HI_U32 ints_tlbinvalid_rd_clr    ); 
HI_VOID VDP_MMU_SetIntsPtwTransClr       ( HI_U32 layer, HI_U32 ints_ptw_trans_clr        ); 
HI_VOID VDP_MMU_SetIntsTlbmissClr        ( HI_U32 layer, HI_U32 ints_tlbmiss_clr          ); 
HI_VOID VDP_MMU_SetIntnsTlbinvalidWrMsk  ( HI_U32 layer, HI_U32 intns_tlbinvalid_wr_msk   ); 
HI_VOID VDP_MMU_SetIntnsTlbinvalidRdMsk  ( HI_U32 layer, HI_U32 intns_tlbinvalid_rd_msk   ); 
HI_VOID VDP_MMU_SetIntnsPtwTransMsk      ( HI_U32 layer, HI_U32 intns_ptw_trans_msk       ); 
HI_VOID VDP_MMU_SetIntnsTlbmissMsk       ( HI_U32 layer, HI_U32 intns_tlbmiss_msk         ); 
HI_VOID VDP_MMU_SetIntnsTlbinvalidWrRaw  ( HI_U32 layer, HI_U32 intns_tlbinvalid_wr_raw   ); 
HI_VOID VDP_MMU_SetIntnsTlbinvalidRdRaw  ( HI_U32 layer, HI_U32 intns_tlbinvalid_rd_raw   ); 
HI_VOID VDP_MMU_SetIntnsPtwTransRaw      ( HI_U32 layer, HI_U32 intns_ptw_trans_raw       ); 
HI_VOID VDP_MMU_SetIntnsTlbmissRaw       ( HI_U32 layer, HI_U32 intns_tlbmiss_raw         ); 
HI_VOID VDP_MMU_SetIntnsTlbinvalidWrStat ( HI_U32 layer, HI_U32 intns_tlbinvalid_wr_stat  ); 
HI_VOID VDP_MMU_SetIntnsTlbinvalidRdStat ( HI_U32 layer, HI_U32 intns_tlbinvalid_rd_stat  ); 
HI_VOID VDP_MMU_SetIntnsPtwTransStat     ( HI_U32 layer, HI_U32 intns_ptw_trans_stat      ); 
HI_VOID VDP_MMU_SetIntnsTlbmissStat      ( HI_U32 layer, HI_U32 intns_tlbmiss_stat        ); 
HI_VOID VDP_MMU_SetIntnsTlbinvalidWrClr  ( HI_U32 layer, HI_U32 intns_tlbinvalid_wr_clr   ); 
HI_VOID VDP_MMU_SetIntnsTlbinvalidRdClr  ( HI_U32 layer, HI_U32 intns_tlbinvalid_rd_clr   ); 
HI_VOID VDP_MMU_SetIntnsPtwTransClr      ( HI_U32 layer, HI_U32 intns_ptw_trans_clr       ); 
HI_VOID VDP_MMU_SetIntnsTlbmissClr       ( HI_U32 layer, HI_U32 intns_tlbmiss_clr         ); 
// HI_VOID VDP_MMU_SetScbTtbrH              ( HI_U32 layer, HI_U32 scb_ttbr_h                ); 
HI_VOID VDP_MMU_SetScbTtbr               ( HI_U32 layer, HI_U32 scb_ttbr                  ); 
// HI_VOID VDP_MMU_SetCbTtbrH               ( HI_U32 layer, HI_U32 cb_ttbr_h                 ); 
HI_VOID VDP_MMU_SetCbTtbr                ( HI_U32 layer, HI_U32 cb_ttbr                   ); 
// HI_VOID VDP_MMU_SetErrSRdAddrH           ( HI_U32 layer, HI_U32 err_s_rd_addr_h           ); 
HI_VOID VDP_MMU_SetErrSRdAddr            ( HI_U32 layer, HI_U32 err_s_rd_addr             ); 
// HI_VOID VDP_MMU_SetErrSWrAddrH           ( HI_U32 layer, HI_U32 err_s_wr_addr_h           ); 
HI_VOID VDP_MMU_SetErrSWrAddr            ( HI_U32 layer, HI_U32 err_s_wr_addr             ); 
// HI_VOID VDP_MMU_SetErrNsRdAddrH          ( HI_U32 layer, HI_U32 err_ns_rd_addr_h          ); 
HI_VOID VDP_MMU_SetErrNsRdAddr           ( HI_U32 layer, HI_U32 err_ns_rd_addr            ); 
// HI_VOID VDP_MMU_SetErrNsWrAddrH          ( HI_U32 layer, HI_U32 err_ns_wr_addr_h          ); 
HI_VOID VDP_MMU_SetErrNsWrAddr           ( HI_U32 layer, HI_U32 err_ns_wr_addr            ); 
// HI_VOID VDP_MMU_SetFaultAddrhPtwS        ( HI_U32 layer, HI_U32 fault_addrh_ptw_s         ); 
HI_VOID VDP_MMU_SetFaultAddrPtwS         ( HI_U32 layer, HI_U32 fault_addr_ptw_s          ); 
HI_VOID VDP_MMU_SetFaultStrmIdS          ( HI_U32 layer, HI_U32 fault_strm_id_s           ); 
HI_VOID VDP_MMU_SetFaultIndexIdS         ( HI_U32 layer, HI_U32 fault_index_id_s          ); 
// HI_VOID VDP_MMU_SetFaultAddrhPtwNs       ( HI_U32 layer, HI_U32 fault_addrh_ptw_ns        ); 
HI_VOID VDP_MMU_SetFaultAddrPtwNs        ( HI_U32 layer, HI_U32 fault_addr_ptw_ns         ); 
HI_VOID VDP_MMU_SetFaultStrmIdNs         ( HI_U32 layer, HI_U32 fault_strm_id_ns          ); 
HI_VOID VDP_MMU_SetFaultIndexIdNs        ( HI_U32 layer, HI_U32 fault_index_id_ns         ); 
HI_VOID VDP_MMU_SetFaultNsPtwNum         ( HI_U32 layer, HI_U32 fault_ns_ptw_num          ); 
HI_VOID VDP_MMU_SetFaultSPtwNum          ( HI_U32 layer, HI_U32 fault_s_ptw_num           ); 
HI_VOID VDP_MMU_SetFaultAddrWrS          ( HI_U32 layer, HI_U32 fault_addr_wr_s           ); 
HI_VOID VDP_MMU_SetFaultTlbWrS           ( HI_U32 layer, HI_U32 fault_tlb_wr_s            ); 
HI_VOID VDP_MMU_SetFaultStrIdWrS         ( HI_U32 layer, HI_U32 fault_str_id_wr_s         ); 
HI_VOID VDP_MMU_SetFaultIndexIdWrS       ( HI_U32 layer, HI_U32 fault_index_id_wr_s       ); 
HI_VOID VDP_MMU_SetFaultAddrWrNs         ( HI_U32 layer, HI_U32 fault_addr_wr_ns          ); 
HI_VOID VDP_MMU_SetFaultTlbWrNs          ( HI_U32 layer, HI_U32 fault_tlb_wr_ns           ); 
HI_VOID VDP_MMU_SetFaultStrIdWrNs        ( HI_U32 layer, HI_U32 fault_str_id_wr_ns        ); 
HI_VOID VDP_MMU_SetFaultIndexIdWrNs      ( HI_U32 layer, HI_U32 fault_index_id_wr_ns      ); 
HI_VOID VDP_MMU_SetFaultAddrRdS          ( HI_U32 layer, HI_U32 fault_addr_rd_s           ); 
HI_VOID VDP_MMU_SetFaultTlbRdS           ( HI_U32 layer, HI_U32 fault_tlb_rd_s            ); 
HI_VOID VDP_MMU_SetFaultStrIdRdS         ( HI_U32 layer, HI_U32 fault_str_id_rd_s         ); 
HI_VOID VDP_MMU_SetFaultIndexIdRdS       ( HI_U32 layer, HI_U32 fault_index_id_rd_s       ); 
HI_VOID VDP_MMU_SetFaultAddrRdNs         ( HI_U32 layer, HI_U32 fault_addr_rd_ns          ); 
HI_VOID VDP_MMU_SetFaultTlbRdNs          ( HI_U32 layer, HI_U32 fault_tlb_rd_ns           ); 
HI_VOID VDP_MMU_SetFaultStrIdRdNs        ( HI_U32 layer, HI_U32 fault_str_id_rd_ns        ); 
HI_VOID VDP_MMU_SetFaultIndexIdRdNs      ( HI_U32 layer, HI_U32 fault_index_id_rd_ns      ); 
HI_VOID VDP_MMU_SetFaultTbuNum           ( HI_U32 layer, HI_U32 fault_tbu_num             ); 
HI_VOID VDP_MMU_SetFaultTlbinvalidErrNs  ( HI_U32 layer, HI_U32 fault_tlbinvalid_err_ns   ); 
HI_VOID VDP_MMU_SetFaultTlbmissErrNs     ( HI_U32 layer, HI_U32 fault_tlbmiss_err_ns      ); 
HI_VOID VDP_MMU_SetFaultTlbinvalidErrS   ( HI_U32 layer, HI_U32 fault_tlbinvalid_err_s    ); 
HI_VOID VDP_MMU_SetFaultTlbmissErrS      ( HI_U32 layer, HI_U32 fault_tlbmiss_err_s       ); 
HI_VOID VDP_MMU_SetReadCommandCounter    ( HI_U32 layer, HI_U32 read_command_counter      ); 
HI_VOID VDP_MMU_SetArchStallN            ( HI_U32 layer, HI_U32 arch_stall_n              ); 
HI_VOID VDP_MMU_SetTbuArreadym           ( HI_U32 layer, HI_U32 tbu_arreadym              ); 
HI_VOID VDP_MMU_SetArReadys              ( HI_U32 layer, HI_U32 ar_readys                 ); 
HI_VOID VDP_MMU_SetArValids              ( HI_U32 layer, HI_U32 ar_valids                 ); 
HI_VOID VDP_MMU_SetWriteCommandCounter   ( HI_U32 layer, HI_U32 write_command_counter     ); 
HI_VOID VDP_MMU_SetAwchStallN            ( HI_U32 layer, HI_U32 awch_stall_n              ); 
HI_VOID VDP_MMU_SetTbuAwreadym           ( HI_U32 layer, HI_U32 tbu_awreadym              ); 
HI_VOID VDP_MMU_SetAwReadys              ( HI_U32 layer, HI_U32 aw_readys                 ); 
HI_VOID VDP_MMU_SetAwValids              ( HI_U32 layer, HI_U32 aw_valids                 ); 
HI_VOID VDP_MMU_SetPrefBufferEmpty       ( HI_U32 layer, HI_U32 pref_buffer_empty         ); 
HI_VOID VDP_MMU_SetPtwq15IdleState       ( HI_U32 layer, HI_U32 ptwq15_idle_state         ); 
HI_VOID VDP_MMU_SetPtwq14IdleState       ( HI_U32 layer, HI_U32 ptwq14_idle_state         ); 
HI_VOID VDP_MMU_SetPtwq13IdleState       ( HI_U32 layer, HI_U32 ptwq13_idle_state         ); 
HI_VOID VDP_MMU_SetPtwq12IdleState       ( HI_U32 layer, HI_U32 ptwq12_idle_state         ); 
HI_VOID VDP_MMU_SetPtwq11IdleState       ( HI_U32 layer, HI_U32 ptwq11_idle_state         ); 
HI_VOID VDP_MMU_SetPtwq10IdleState       ( HI_U32 layer, HI_U32 ptwq10_idle_state         ); 
HI_VOID VDP_MMU_SetPtwq9IdleState        ( HI_U32 layer, HI_U32 ptwq9_idle_state          ); 
HI_VOID VDP_MMU_SetPtwq8IdleState        ( HI_U32 layer, HI_U32 ptwq8_idle_state          ); 
HI_VOID VDP_MMU_SetPtwq7IdleState        ( HI_U32 layer, HI_U32 ptwq7_idle_state          ); 
HI_VOID VDP_MMU_SetPtwq6IdleState        ( HI_U32 layer, HI_U32 ptwq6_idle_state          ); 
HI_VOID VDP_MMU_SetPtwq5IdleState        ( HI_U32 layer, HI_U32 ptwq5_idle_state          ); 
HI_VOID VDP_MMU_SetPtwq4IdleState        ( HI_U32 layer, HI_U32 ptwq4_idle_state          ); 
HI_VOID VDP_MMU_SetPtwq3IdleState        ( HI_U32 layer, HI_U32 ptwq3_idle_state          ); 
HI_VOID VDP_MMU_SetPtwq2IdleState        ( HI_U32 layer, HI_U32 ptwq2_idle_state          ); 
HI_VOID VDP_MMU_SetPtwq1IdleState        ( HI_U32 layer, HI_U32 ptwq1_idle_state          ); 
HI_VOID VDP_MMU_SetPtwq0IdleState        ( HI_U32 layer, HI_U32 ptwq0_idle_state          ); 
HI_VOID VDP_MMU_SetSmmuRstState          ( HI_U32 layer, HI_U32 smmu_rst_state            ); 
HI_VOID VDP_MMU_SetInOutCmdCntRd         ( HI_U32 layer, HI_U32 in_out_cmd_cnt_rd         ); 
HI_VOID VDP_MMU_SetRdyDebugRd            ( HI_U32 layer, HI_U32 rdy_debug_rd              ); 
HI_VOID VDP_MMU_SetVldDebugRd            ( HI_U32 layer, HI_U32 vld_debug_rd              ); 
HI_VOID VDP_MMU_SetCurMissCntRd          ( HI_U32 layer, HI_U32 cur_miss_cnt_rd           ); 
HI_VOID VDP_MMU_SetLastMissCntRd         ( HI_U32 layer, HI_U32 last_miss_cnt_rd          ); 
HI_VOID VDP_MMU_SetInOutCmdCntWr         ( HI_U32 layer, HI_U32 in_out_cmd_cnt_wr         ); 
HI_VOID VDP_MMU_SetRdyDebugWr            ( HI_U32 layer, HI_U32 rdy_debug_wr              ); 
HI_VOID VDP_MMU_SetVldDebugWr            ( HI_U32 layer, HI_U32 vld_debug_wr              ); 
HI_VOID VDP_MMU_SetCurMissCntWr          ( HI_U32 layer, HI_U32 cur_miss_cnt_wr           ); 
HI_VOID VDP_MMU_SetLastMissCntWr         ( HI_U32 layer, HI_U32 last_miss_cnt_wr          ); 
HI_VOID VDP_MMU_SetCurDoubleUpdCntRd     ( HI_U32 layer, HI_U32 cur_double_upd_cnt_rd     ); 
HI_VOID VDP_MMU_SetLastDoubleUpdCntRd    ( HI_U32 layer, HI_U32 last_double_upd_cnt_rd    ); 
HI_VOID VDP_MMU_SetCurDoubleMissCntRd    ( HI_U32 layer, HI_U32 cur_double_miss_cnt_rd    ); 
HI_VOID VDP_MMU_SetLastDoubleMissCntRd   ( HI_U32 layer, HI_U32 last_double_miss_cnt_rd   ); 
HI_VOID VDP_MMU_SetMstFsmCur             ( HI_U32 layer, HI_U32 mst_fsm_cur               ); 
HI_VOID VDP_MMU_SetCurDoubleUpdCntWr     ( HI_U32 layer, HI_U32 cur_double_upd_cnt_wr     ); 
HI_VOID VDP_MMU_SetLastDoubleUpdCntWr    ( HI_U32 layer, HI_U32 last_double_upd_cnt_wr    ); 
HI_VOID VDP_MMU_SetCurDoubleMissCntWr    ( HI_U32 layer, HI_U32 cur_double_miss_cnt_wr    ); 
HI_VOID VDP_MMU_SetLastDoubleMissCntWr   ( HI_U32 layer, HI_U32 last_double_miss_cnt_wr   ); 
HI_VOID VDP_MMU_SetLastSel1ChnMissCntRd  ( HI_U32 layer, HI_U32 last_sel1_chn_miss_cnt_rd ); 
HI_VOID VDP_MMU_SetCurSel1ChnMissCntRd   ( HI_U32 layer, HI_U32 cur_sel1_chn_miss_cnt_rd  ); 
HI_VOID VDP_MMU_SetLastSel2ChnMissCntRd  ( HI_U32 layer, HI_U32 last_sel2_chn_miss_cnt_rd ); 
HI_VOID VDP_MMU_SetCurSel2ChnMissCntRd   ( HI_U32 layer, HI_U32 cur_sel2_chn_miss_cnt_rd  ); 
HI_VOID VDP_MMU_SetLastSel1ChnMissCntWr  ( HI_U32 layer, HI_U32 last_sel1_chn_miss_cnt_wr ); 
HI_VOID VDP_MMU_SetCurSel1ChnMissCntWr   ( HI_U32 layer, HI_U32 cur_sel1_chn_miss_cnt_wr  ); 
HI_VOID VDP_MMU_SetLastSel2ChnMissCntWr  ( HI_U32 layer, HI_U32 last_sel2_chn_miss_cnt_wr ); 
HI_VOID VDP_MMU_SetCurSel2ChnMissCntWr   ( HI_U32 layer, HI_U32 cur_sel2_chn_miss_cnt_wr  ); 
HI_VOID VDP_MMU_SetSel1ChnRd             ( HI_U32 layer, HI_U32 sel1_chn_rd               ); 
HI_VOID VDP_MMU_SetSel2ChnRd             ( HI_U32 layer, HI_U32 sel2_chn_rd               ); 
HI_VOID VDP_MMU_SetSel1ChnWr             ( HI_U32 layer, HI_U32 sel1_chn_wr               ); 
HI_VOID VDP_MMU_SetSel2ChnWr             ( HI_U32 layer, HI_U32 sel2_chn_wr               ); 

#endif

